1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Background Art
Conventional T-CAMs (Ternary Contents Addressable Memories) generally use SRAMs (Static Random Access Memories) as their memories for storing information, and such T-CAMs have been available commercially. However, each cell of this type of T-CAM using SRAMs requires as many as 16 transistors (6 transistors for each of the two CMOS-SRAMs and 4 xe2x80x9csearch transistorsxe2x80x9d), resulting in increased cell area.
To solve the above problem, attempts have been made to adopt DRAMs (Dynamic Random Access Memories) for the storage memory section, as described in, for example, U.S. Pat. Nos. 6,320.777 and 6,262,907.
FIG. 18 shows a diagram (originally FIG. 7A) taken from the above U.S. Pat. No. 6,320.777 for reference, illustrating the layout of a half-bit memory cell of a T-CAM.
Referring to FIG. 18, the memory cell includes a diffusion layer 1801 for a DRAM storage memory of one bit and a diffusion layer 1802 for search transistors. Reference numeral 1803 denotes a word line; 1804 denotes the gate electrode of a search transistor turned on and off by the information stored in the storage memory; and 1805 denotes the gate electrode of another search transistor turned on and off through a search line. Reference numeral 1806 denotes a storage node contact hole which connects between the memory cell transistor diffusion layer 1801, which has the word line 1803, and a storage node 1814. Furthermore, reference numerals 1807 to 1812 denotes contact holes formed in a process different from that for the storage node contact hole 1806.
The potential written in (applied to and held by) the storage node 1814 is transmitted to the search transistor gate electrode 1804 through a wire 1813 and a contact hole 1808 from the contact hole 1807 in the diffusion layer 1801 in which the storage node contact hole 1806 is also formed.
Further referring to FIG. 18, the contact holes 1809 to 1812 are connected to a bit line, a discharge line, a match line, and a search line (all not shown), respectively.
Only when the search transistor with the gate electrode 1804 is turned on by a high state (potential) written in the storage node 1814 and furthermore the search line (not shown) is set to a high state (potential) for search operation, are the two series-connected search transistors turned on at the same time. This turning-on of the two search transistors connects between the precharged match line and the discharge line, so that the potential of the match line is brought to that of the discharge line. Otherwise, since at least one of the two search transistors is off, the potential of the match line does not change. Each unit cell of a CAM is made up of a single cell operating as described above, while each unit cell of a T-CAM is made up of two cells each operating as described above.
The cell area of T-CAMs can be reduced to some extent by using DRAMs as their storage memories, instead of SRAMs. However, it is desirable to further reduce the cell area.
The arrangement shown in FIG. 18, however, employs one storage node contact hole (1806), two contact holes (1807, 1808), and a wire (1813) in order to set the storage node 1814 and the search transistor gate electrode 1804 at the same potential. Therefore, it is not possible to further reduce the cell area since the layout space for these contact holes and the wire must be provided.
Furthermore, in the manufacturing process of (such) semiconductor devices, it is necessary to open all of the storage node contact hole 1806 and the contact holes 1807 and 1808 as well as preventing shorting between the wire 1813 and other wires. Therefore, the above layout is disadvantageous also from the viewpoint of production yield.
The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of reducing the layout area for connecting between the storage node and the gate electrode having the same potential as the storage node
Another purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of realizing high production yield by a simple structure.
Other purposes and advantages of the present invention will become apparent from the following description.
According to one aspect of the present invention, a semiconductor device comprises a diffusion layer formed in a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film, an interlayer insulation film formed on the semiconductor substrate so as to cover the gate electrode, and a capacitor formed on the interlayer insulation film and having a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion layer, the gate electrode, and the lower electrode are connected to one another by a common contact formed in the interlayer insulation film.
According to another aspect of the present invention, in a method for manufacturing a semiconductor device, a P-well region is formed in a semiconductor substrate. A gate insulation film is formed on the P-well region. A gate electrode is formed on the gate insulation film. A diffusion layer is formed in the P-well region of both sides of the gate electrode. The diffusion layer is used as a source/drain region. A sidewall is formed on both sides of the gate electrode and the gate insulation film. An insulation film is deposited on the diffusion layer, thereby an interlayer insulation film for covering the gate electrode and the sidewall is obtained. The interlayer insulation film is etched to form a contact hole reaching the diffusion layer and the gate electrode. The contact hole is filled with an impurity doped polysilicon to form a contact. A lower electrode, a dielectric film, and an upper electrode are laminated on the contact in that order to form a capacitor.
According to other aspect of the present invention, in a method for manufacturing a semiconductor device, a P-well region is formed in a semiconductor substrate. A gate insulation film is formed on the P-well region. A gate electrode is formed on the gate insulation film. A shallow diffusion layer is formed in the P-well region of both sides of the gate electrode. The shallow diffusion layer is used as a source/drain region. A sidewall is formed on both sides of the gate electrode and the gate insulation film after the step of forming the shallow diffusion layer. A deep diffusion layer is formed in the P-well region of both sides of the sidewall. The deep diffusion layer is used as a source/drain region. The tops of the deep diffusion layer and the gate electrode are silicifyed. An insulation film is deposited on the deep diffusion layer, thereby an interlayer insulation film for covering the gate electrode and the sidewall is obtained. The interlayer insulation film is etched to form a contact hole reaching the deep diffusion layer and the gate electrode. The barrier metal layer is formed inside the contact hole. The contact hole is filled with tungsten to form a contact. A lower electrode, a dielectric film, and an upper electrode are laminated on the contact in that order to form a capacitor.
Other and further objects, features and advantages of the invention will appear more fully from the following description.